	RALINK_REG(0xbe005648)=0xc0005ab2;
	RALINK_REG(0xbe005640)=0x00000223;
	RALINK_REG(0xbe005604)=0x00040002;
	udelay_a(1*oneusec);
	RALINK_REG(0xbe005604)=0x00040003;
	udelay_a(2*oneusec);
	RALINK_REG(0xbe005600)=0x0c041981;
	RALINK_REG(0xbe005600)=0x0e041981;
	udelay_a(20*oneusec);
	RALINK_REG(0xbe00560c)=0x00080440;
	RALINK_REG(0xbe00560c)=0x00090440;
	udelay_a(2*oneusec);
	RALINK_REG(0xbe005600)=0x0e041985;
	udelay_a(20*oneusec);
if (((RALINK_REG(0xBE000010)>>6)&0x7)<3) { 
/* XTAL=20MHZ */ 
	RALINK_REG(0xbe005604)=0x00040101;
	udelay_a(1*oneusec);
	RALINK_REG(0xbe005648)=0xc0004ab2;
#if defined (MEMPLL_CLK_600) 
	RALINK_REG(0xbe005618)=0xc00008f8;
	RALINK_REG(0xbe005624)=0xc00008f8;
	RALINK_REG(0xbe005630)=0xc00008f8;
	RALINK_REG(0xbe005618)=0xc20008f8;
	RALINK_REG(0xbe005624)=0xc20008f8;
	RALINK_REG(0xbe005630)=0xc20008f8;
#elif defined (MEMPLL_CLK_400) 
	RALINK_REG(0xbe005618)=0xc00008ab;
	RALINK_REG(0xbe005624)=0xc00008ab;
	RALINK_REG(0xbe005630)=0xc00008ab;
	RALINK_REG(0xbe005618)=0xc20008ab;
	RALINK_REG(0xbe005624)=0xc20008ab;
	RALINK_REG(0xbe005630)=0xc20008ab;
#elif defined (MEMPLL_CLK_200) 
	RALINK_REG(0xbe005618)=0xc400085a;
	RALINK_REG(0xbe005624)=0xc400085a;
	RALINK_REG(0xbe005630)=0xc400085a;
	RALINK_REG(0xbe005618)=0xc600085a;
	RALINK_REG(0xbe005624)=0xc600085a;
	RALINK_REG(0xbe005630)=0xc600085a;
#else 
#error "MEMPLL clock not defined" 
#endif 
	RALINK_REG(0xbe005648)=0xc0004ab2;
	udelay_a(20*oneusec);
	RALINK_REG(0xbe005640)=0x00000233;
}else if (((RALINK_REG(0xBE000010)>>6)&0x7)<6) { 
/* XTAL=40MHZ */ 
	RALINK_REG(0xbe005604)=0x00040103;
	udelay_a(1*oneusec);
	RALINK_REG(0xbe005648)=0xc0005ab2;
#if defined (MPLL_IN_LBK) 
/* if MEPLL internal loopback */ 
#if defined (MEMPLL_CLK_600) 
	RALINK_REG(0xbe005618)=0xc00009e2;
	RALINK_REG(0xbe005624)=0xc00009e2;
	RALINK_REG(0xbe005630)=0xc00009e2;
	RALINK_REG(0xbe005618)=0xc20009e2;
	RALINK_REG(0xbe005624)=0xc20009e2;
	RALINK_REG(0xbe005630)=0xc20009e2;
#elif defined (MEMPLL_CLK_400) 
	RALINK_REG(0xbe005618)=0xc0000942;
	RALINK_REG(0xbe005624)=0xc0000942;
	RALINK_REG(0xbe005630)=0xc0000942;
	RALINK_REG(0xbe005618)=0xc2000942;
	RALINK_REG(0xbe005624)=0xc2000942;
	RALINK_REG(0xbe005630)=0xc2000942;
#elif defined (MEMPLL_CLK_200) 
	RALINK_REG(0xbe005618)=0xc4000942;
	RALINK_REG(0xbe005624)=0xc4000942;
	RALINK_REG(0xbe005630)=0xc4000942;
	RALINK_REG(0xbe005618)=0xc6000942;
	RALINK_REG(0xbe005624)=0xc6000942;
	RALINK_REG(0xbe005630)=0xc6000942;
#else 
#error "MEMPLL clock not defined" 
#endif 
	RALINK_REG(0xbe005648)=0xc2005ab2;
	udelay_a(20*oneusec);
	RALINK_REG(0xbe005640)=0x00000233;
#else /* else MEPLL external loopback */ 
#if defined (MEMPLL_CLK_600) 
	RALINK_REG(0xbe005618)=0xc00008fa;
	RALINK_REG(0xbe005624)=0xc00008fa;
	RALINK_REG(0xbe005630)=0xc00008fa;
	RALINK_REG(0xbe005624)=0xc20008fa;
	RALINK_REG(0xbe005630)=0xc20008fa;
#elif defined (MEMPLL_CLK_400) 
	RALINK_REG(0xbe005618)=0xc00008aa;
	RALINK_REG(0xbe005624)=0xc00008aa;
	RALINK_REG(0xbe005630)=0xc00008aa;
	RALINK_REG(0xbe005618)=0xc20008aa;
	RALINK_REG(0xbe005624)=0xc20008aa;
	RALINK_REG(0xbe005630)=0xc20008aa;
#elif defined (MEMPLL_CLK_200) 
	RALINK_REG(0xbe005618)=0xc400085a;
	RALINK_REG(0xbe005624)=0xc400085a;
	RALINK_REG(0xbe005630)=0xc400085a;
	RALINK_REG(0xbe005618)=0xc600085a;
	RALINK_REG(0xbe005624)=0xc600085a;
	RALINK_REG(0xbe005630)=0xc600085a;
#else 
#error "MEMPLL clock not defined" 
#endif 
	RALINK_REG(0xbe005648)=0xc2005ab2;
	udelay_a(20*oneusec);
	RALINK_REG(0xbe005640)=0x00000233;
#endif /* end of MPLL_IN_LBK */ 
}else{ 
/* XTAL=25MHZ */ 
	RALINK_REG(0xbe005604)=0x00040101;
	udelay_a(1*oneusec);
	RALINK_REG(0xbe005648)=0xc0004a22;
#if defined (MEMPLL_CLK_600) 
	RALINK_REG(0xbe005618)=0xc00008c8;
	RALINK_REG(0xbe005624)=0xc00008c8;
	RALINK_REG(0xbe005630)=0xc00008c8;
	RALINK_REG(0xbe005618)=0xc20008c8;
	RALINK_REG(0xbe005624)=0xc20008c8;
	RALINK_REG(0xbe005630)=0xc20008c8;
#elif defined (MEMPLL_CLK_400) 
	RALINK_REG(0xbe005618)=0xc000088a;
	RALINK_REG(0xbe005624)=0xc000088a;
	RALINK_REG(0xbe005630)=0xc000088a;
	RALINK_REG(0xbe005618)=0xc200088a;
	RALINK_REG(0xbe005624)=0xc200088a;
	RALINK_REG(0xbe005630)=0xc200088a;
#elif defined (MEMPLL_CLK_200) 
	RALINK_REG(0xbe005618)=0xc400084a;
	RALINK_REG(0xbe005624)=0xc400084a;
	RALINK_REG(0xbe005630)=0xc400084a;
	RALINK_REG(0xbe005618)=0xc600084a;
	RALINK_REG(0xbe005624)=0xc600084a;
	RALINK_REG(0xbe005630)=0xc600084a;
#else 
#error "MEMPLL clock not defined" 
#endif 
	RALINK_REG(0xbe005648)=0xc2004a22;
	udelay_a(20*oneusec);
	RALINK_REG(0xbe005640)=0x00000233;
} 
